Method and Apparatus for USB Periodic Scheduling Optimization

ABSTRACT

A computerized system is disclosed. The computerized system may include one or more processors configured to perform the operations stored in a memory. The operations may include sorting a subset of a plurality of endpoints for communication during a communication frame first based on service interval time assigned to each endpoint and then resorting based on a concurrency score of each peripheral device corresponding to the subset of the plurality of endpoints. The operations may include determining available bandwidth and a number of packets to be communicated with the each endpoint of the subset of the plurality of endpoints. The operations may include generating a scheduling table that includes the number of packets and an order of communication of the packets to be communicated with the each endpoint of the subset of the plurality of endpoints.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of Indian Patent Appl. No.201811048587, filed on Dec. 21, 2018, which is incorporated herein byreference in its entirety for all purposes.

COPYRIGHT NOTICE

The assignee of this patent document has no objection to the facsimilereproduction by anyone of the patent document itself, or of the patentapplication, as it appears in the files of the United States Patent andTrademark Office, but otherwise reserves all rights whatsoever in anyincluded works of authorship protected by copyright.

SPECIFICATION—DISCLAIMERS

In the following Background, Summary, and Detailed Description,paragraph headings do not signify limitations. In these writings, thecitation or identification of any publication signifies neitherrelevance nor status as prior art. Many paragraphs in this disclosureare common to multiple Synopsys patent specifications.

FIELD(S) OF TECHNOLOGY

The following information is solely for use in searching the prior art.This disclosure has significance in the field of electronics in general,including the following topics: electronic design automation, universalserial bus (USB) scheduling, and USB periodic scheduling.

BACKGROUND

USB is a widely used interconnect standard. A USB system consists of aUSB host, and one or more USB peripherals. A USB peripheral can be a USBdevice or a USB hub. The USB host is responsible for initiating all datatransfers in the USB system. Each USB peripheral has one or moreendpoints used for data transfers. The one or more endpoints on the USBperipheral are hardware based. An endpoint on the USB host is softwarebased. The USB host can send data to an OUT endpoint of a USB peripheralthat is generally referenced as a data sink. The USB host can receivedata from an IN endpoint of a USB peripheral that is generallyreferenced as a data source.

IN and OUT endpoints are further divided into two categories: periodicendpoints and non-periodic endpoints. These two types of endpoints havedifferent scheduling requirements for the USB host. Periodic endpointsrequire the host to schedule transfers periodically within a specifiedtime interval, but non-periodic endpoints do not have such a constraint;they receive or send data at the best effort of the host. In otherwords, the host sends or receives data from a non-periodic endpointwhenever there is USB bus bandwidth available.

The USB host performs scheduling to meet requirements of periodicendpoints according to bandwidth requirements of the periodic endpoints.Accordingly, USB bus utilization and overall USB system performance islargely dependent on the efficiency of USB periodic scheduling. Inaddition, the latest USB standard USB3.2 supports four (4) more highdata rates along with speeds supported by USB2.0 standard. The four newhigh data rates in USB3.2 standard are five (5) Giga bits per second(Gbps) for Gen 1x1, ten (10) Gbps for Gen2x1, 2x5 Gbps for Gen1x2, and20 Gbps for Gen2x2. Due to high data rates supported by USB3.2 standard,any inefficient resulted from the host periodic scheduling leads to lossof the data throughput and the degradation of the USB systemperformance.

SUMMARY

This Summary is a prelude to the Detailed Description. This Summary,together with the independent Claims, signifies a brief writing about atleast one claimed invention (which can be a discovery, see 35 USC100(a); and see 35 USC 100(j)), for use in commerce that is enabled bythe Specification and Drawings.

The claims signify a brief description of one or more of theinnovations, embodiments, and/or examples found within this disclosure.

This disclosure describes a computerized system for USB periodicscheduling optimization. The computerized system may include a memoryconfigured to store operations, and one or more processors configured toperform the operations including sorting a subset of a plurality ofendpoints for communication during a communication frame. The subset ofthe plurality of endpoints may be sorted based on a value of serviceinterval assigned to each endpoint of the subset of the plurality ofendpoints. The plurality of endpoints may include one or more endpointsof a first peripheral device and one or more endpoints of a secondperipheral device. The operations may further include re-sorting thesorted subset of the plurality of endpoints based on a concurrency scoreof the first peripheral device with the second peripheral device. Theoperations may also include determining available bandwidth forcommunication with the each endpoint of the subset of the plurality ofendpoints. The operations may further include determining a number ofpackets to be communicated with the each endpoint of the subset of theplurality of endpoints based on the determined available bandwidth andgenerating a scheduling table for communicating the number of packetswith the each endpoint of the subset of the plurality of endpoints basedon the concurrency score of the first peripheral device with the secondperipheral device. The generated scheduling table may include the numberof packets to be communicated with the each endpoint of the subset ofthe plurality of endpoints and an order of communication of the numberof packets to be communicated with the each endpoint of the subset ofthe plurality of endpoints.

This disclosure also describes a method for USB periodic schedulingoptimization. The method may include sorting a subset of a plurality ofendpoints for communication during a communication frame. The subset ofthe plurality of endpoints may be sorted based on a value of serviceinterval assigned to each endpoint of the subset of the plurality ofendpoints. The plurality of endpoints may include one or more endpointsof a first peripheral device and one or more endpoints of a secondperipheral device. The method may further include re-sorting the sortedsubset of the plurality of endpoints based on a concurrency score of thefirst peripheral device with the second peripheral device. The methodmay also include determining available bandwidth for communication withthe each endpoint of the subset of the plurality of endpoints. Themethod may further include determining a number of packets to becommunicated with the each endpoint of the subset of the plurality ofendpoints based on the determined available bandwidth and generating ascheduling table for communicating the number of packets with the eachendpoint of the subset of the plurality of endpoints based on theconcurrency score of the first peripheral device with the secondperipheral device. The generated scheduling table may include the numberof packets to be communicated with the each endpoint of the subset ofthe plurality of endpoints and an order of communication of the numberof packets to be communicated with the each endpoint of the subset ofthe plurality of endpoints.

This disclosure also describes a non-transitory computer-readable devicehaving instructions stored thereon that, when executed by at least onecomputing device, causes the at least one computing device to performoperations including sorting a subset of a plurality of endpoints forcommunication during a communication frame. The subset of the pluralityof endpoints may be sorted based on a value of service interval assignedto each endpoint of the subset of the plurality of endpoints. Theplurality of endpoints may include one or more endpoints of a firstperipheral device and one or more endpoints of a second peripheraldevice. The operations may further include re-sorting the sorted subsetof the plurality of endpoints based on a concurrency score of the firstperipheral device with the second peripheral device. The operations mayalso include determining available bandwidth for communication with theeach endpoint of the subset of the plurality of endpoints. Theoperations may further include determining a number of packets to becommunicated with the each endpoint of the subset of the plurality ofendpoints based on the determined available bandwidth and generating ascheduling table for communicating the number of packets with the eachendpoint of the subset of the plurality of endpoints based on theconcurrency score of the first peripheral device with the secondperipheral device.

This Summary does not completely signify the claimed inventions. ThisSummary (as well as the Abstract) neither signifies essential elementsof, nor limits the scope of, the claimed inventions enabled by theSpecification and Figures.

DRAWINGS

The following Detailed Description, Figures, and Claims signify the usesand advantages of the claimed inventions, and their embodiments. All ofthe Figures are used only to provide knowledge and understanding and donot limit the scope of the claimed inventions and their embodiments.Such Figures are not necessarily drawn to scale.

Similar components or features used in the Figures can have the same, orsimilar, reference signs in the form of labels (such as alphanumericsymbols, e.g., reference numerals), and can signify a similar orequivalent use. Further, various components of the same type can bedistinguished by following the reference label by a dash and a secondlabel that distinguishes among the similar components. If only the firstreference label is used in the Specification, its use applies to anysimilar component having the same first reference label irrespective ofthe second reference label. A brief description of the Figures is below.

FIG. 1 illustrates a USB3.2 network topology, according to an exemplaryembodiment of the present disclosure.

FIG. 2 illustrates sequential data transfers, according to an exemplaryembodiment of the present disclosure.

FIG. 3 illustrates concurrent data transfers, according to an exemplaryembodiment of the present disclosure.

FIG. 4 illustrates a USB3.2 network topology, according to an exemplaryembodiment of the present disclosure.

FIG. 5 illustrates bandwidth domains, according to an exemplaryembodiment of the present disclosure.

FIG. 6 illustrates bandwidth domains, according to an exemplaryembodiment of the present disclosure.

FIG. 7 illustrates bandwidth domains, according to an exemplaryembodiment of the present disclosure.

FIG. 8 illustrates periodic endpoint list sorted by service intervals(SIs), according to an exemplary embodiments of the present disclosure.

FIG. 9 illustrates periodic endpoint list sorted by Sis and adjustedbased on concurrency scores, according to an exemplary embodiments ofthe present disclosure.

FIG. 10 illustrates an order of scheduling tokens, according to anexemplary embodiment of the present disclosure.

FIG. 11 illustrates an order of scheduling tokens adjusted based onconcurrent scores, according to an exemplary embodiments of the presentdisclosure.

FIG. 12 illustrates a flow diagram of USB host periodic scheduling,according to an exemplary embodiment of the present disclosure.

FIG. 13 illustrates a flow-chart of various processes used during thedesign and fabrication of an integrated circuit, according to anexemplary embodiments of the present disclosure.

FIGS. 14A and 14B illustrate abstract diagrams of a computer system foruse in commerce, if needed, by embodiments of the claimed inventions, aswell as an embodiment of a circuit design and an embodiment of amanufactured circuit used in these claimed inventions.

In the Figures, reference signs can be omitted as is consistent withaccepted engineering practice; however, a skilled person will understandthat the illustrated components are readily understood when viewed inthe context of the illustration as a whole and the accompanyingdisclosure describing such various figures.

DETAILED DESCRIPTION

The Figures and Detailed Description signify, only to provide knowledgeand understanding, the claimed inventions. To minimize the length of theDetailed Description, while various features, structures orcharacteristics can be described together in a single embodiment, theyalso can be used in other embodiments without being written about.Variations of any of these elements, and modules, processes, machines,systems, manufactures or compositions disclosed by such embodimentsand/or examples are easily used in commerce. The Figures and DetailedDescription also can signify, implicitly or explicitly, advantages andimprovements of the claimed inventions and their embodiments for use incommerce.

In the Figures and Detailed Description, numerous specific details canbe described to enable at least one embodiment of the claimedinventions. Any embodiment disclosed herein signifies a tangible form ofa claim invention. To not obscure the significance of the embodimentsand/or examples in this Detailed Description, some elements that areknown to a skilled person can be combined together for presentation andfor illustration purposes and not be described in detail. To not obscurethe significance of these embodiments and/or examples, some well-knownprocesses, machines, systems, manufactures or compositions are notwritten about in detail. However, a skilled person can use theseembodiments and/or examples in commerce without these specific detailsor their equivalents. Thus, the Detailed Description focuses on enablingthe distinctive elements of the claimed inventions and exemplaryembodiments. Where this Detailed Description refers to some elements inthe singular tense, more than one element can be depicted in the Figuresand like elements are labeled with like numerals.

Detailed Description—a Simple USB 3.2 Network Topology

USB3.2 is the latest USB standard that supports four new high speed datarates, namely 5 Giga bits per second for Gen 1x1, 10 Giga bits persecond for Gen2x1, 2x5 Giga bits per second for Gen1x2 and 20 Giga bitsper second for Gen2x2. A USB network comprises a USB host and one ormore USB peripheral devices. A USB peripheral device may be USB devicesor a USB hub. The peripheral device may have a plurality of endpoints.An endpoint of the peripheral device may be an OUT endpoint or an INendpoint. The USB host sends data to the OUT endpoint, also referencedin this disclosure as a data sink, of the USB peripheral device andreceives data from the IN endpoint, also referenced in this disclosureas a data source, of the USB peripheral device. In other words, the USBhost is responsible for initiating all data transfers in the USBnetwork.

The IN and OUT endpoints may be either periodic endpoints ornon-periodic endpoints. The USB host may need to satisfy schedulingrequirements for the periodic and non-periodic endpoints differently.Periodic endpoints require the USB host to schedule transfersperiodically with a specified time interval. However, non-periodicendpoints do not require the USB host to schedule periodic transfersrather only require that they receive or send data at the best effort ofthe USB host.

Periodic scheduling is a process in which for every micro frame, the USBhost determines an ordered list of periodic endpoints. A successfulperiodic scheduling by the USB host must meet the following tworequirements. First, all the periodic endpoints need to be served withinthe endpoint service interval time (ESIT) with a maximum ESIT payload.Second, USB bus bandwidth limit should not be exceeded.

FIG. 1 illustrates a USB3.2 network topology, according to an exemplaryembodiment of the present disclosure. In some embodiments, A USB3.2 host102 and USB peripheral devices such as a USB3.2 hub 104, a firstperipheral device Dev1 106, and a second peripheral device Dev2 108 areshown in FIG. 1. The first peripheral device Dev1 106 has twoisochronous IN endpoints EP1 106 a and EP2 106 b. Similarly, the secondperipheral device Dev2 108 has two isochronous IN endpoints EP1 108 aand EP2 108 b. The USB peripheral devices such as the USB3.2 hub 104,the first peripheral device Dev1 106, and the second peripheral deviceDev2 108 are communicatively coupled with each other via one or morebuses. For example, the USB3.2 hub 104 is communicatively coupled withthe USB3.2 host 102 via a bus Bus1 110. The first peripheral device Dev1106 and the second peripheral device Dev2 108 are communicativelycoupled with the USB3.2 hub 104 via a bus Bus2 114 and a bus Bus3 112respectively. The buses Bus1 110, Bus2 114, and Bus3 112 may eachsupport one of the high speed data rate described above. By way ofnon-limiting example, the bus Bus1 110 is of type GEN2x2 that supports20 Gbps data speed and the buses Bus2 114 and Bus3 112 each is of typeGen2X1 that supports 10 Gbps data speed. Further, by way of non-limitingexample, service interval time for the two isochronous IN endpoints EP1106 a and EP2 106 b of the first peripheral device Dev1 106 and the twoisochronous IN endpoints EP1 108 a and EP2 108 b of the secondperipheral device Dev 108 may be zero (0), i.e., the IN endpoints 106 a,106 b, 108 a, and 108 b are required to be served in every micro frame.As described in “eXtensible Host Controller Interface for UniversalSerial Bus (xHCI),” revision 1.1, which is incorporated herein byreference in its entirety for all purposes, the IN endpoints 106 a, 106b, 108 a, and 108 b may be configured for number of bytes allowed fortransfer during a micro frame based on “max burst size” and “mult”fields' values. While FIG. 1 shows a USB3.2 system and variousembodiments are described herein with respect to the USB3.2 system,various embodiments as described herein may also be applied to USBsystem according to other USB standards and/or other types of networkfor scheduling and optimization.

FIG. 2 illustrates sequential data transfers, according to an exemplaryembodiment of the present disclosure. As described above, the USB hostis responsible for initiating and scheduling data transfers in the USBsystem. In some embodiments, by way of non-limiting example, a USB3.2host 202 and a USB3.2 hub 204 are communicatively coupled with eachother via a GEN2x2 USB bus Bus1 210, which supports high speed data rateof 20 Gbps. A first peripheral device Dev1 206 with two isochronous INendpoints EP1 206 a and EP2 206 b and a second peripheral device Dev2208 with two isochronous IN endpoints EP1 208 a and EP2 208 b are shown.The first peripheral device Dev1 206 and the second peripheral deviceDev2 208 are each communicatively coupled with the USB3.2 hub 204 via aGEN2x1 bus Bus2 214 and a GEN2x1 bus Bus3 212 respectively. By way ofnon-limiting example, the USB3.2 host 202 may schedule the IN datatransfer in the following order: EP1 206 a, EP2 206 b, EP1 208 a, EP2208 b. When the USB3.2 host 202 schedules IN data transfer according tothe above described order, as shown in FIG. 2, there would be gapsbetween two consecutive data transfers. The gaps between the twoconsecutive data transfer bursts occur because the bus Bus1 210 is twiceas fast as the buses Bus2 214 and Bus3 212 each and because of thescheduling order as described above. It is clear as can be seen from theFIG. 2 that scheduling of the IN data transfer according to an order asmay result in an inefficient bandwidth usage of the USB system.

FIG. 3 illustrates concurrent data transfers, according to an exemplaryembodiment of the present disclosure. In some embodiments, by way ofnon-limiting example, a USB3.2 host 302 and a USB3.2 hub 304 arecommunicatively coupled with each other via a GEN2x2 USB bus Bus1 310,which supports high speed data rate of 20 Gbps. A first peripheraldevice Dev1 306 with two isochronous IN endpoints EP1 306 a and EP2 306b and a second peripheral device Dev2 308 with two isochronous INendpoints EP1 308 a and EP2 308 b are shown. The first peripheral deviceDev1 306 and the second peripheral device Dev2 308 are eachcommunicatively coupled with the USB3.2 hub 304 via a GEN2x1 bus Bus2312 and a GEN2x1 bus Bus3 314 respectively. By way of non-limitingexample, the USB3.2 host 302 may schedule the IN data transfer in thefollowing order: EP1 206 a, EP1 208 a, EP2 206 b, EP2 208 b. When theUSB3.2 host 202 schedules IN data transfer according to the abovedescribed order, as shown in FIG. 3, there would be no gap between twoconsecutive data transfers if the USB3.2 host 302 supports at least four(4) outstanding IN transfers. Thus, scheduling of the IN data transferaccording to an order as described with reference to FIG. 3 may resultin an efficient bandwidth usage of the USB system in comparison with theIN data transfer according to an order as described with reference toFIG. 2.

Detailed Description—Scheduling Optimization for a USB 3.2 NetworkTopology—Bandwidth Domains

FIG. 4 illustrates a USB3.2 network topology, according to an exemplaryembodiment of the present disclosure. The USB3.2 network as shown inFIG. 4 is complex in comparison with the USB3.2 network shown in any ofthe FIG. 1 through FIG. 3. In some embodiments, by way of non-limitingexample, as shown in FIG. 4, the USB3.2 network may comprise a USB3.2host 402, and a plurality of peripheral devices. The plurality ofperipheral devices comprise peripheral devices Dev1 406, Dev2 408, Dev3410, Dev4 412, Dev5 414, Dev6 416, Dev7 418, Dev8 420, Dev9 422, andDev10 424. The plurality of peripheral devices also comprise USB3.2 hubshub1 404, hub2 426, hub3 428, and hub4 430. The plurality of peripheraldevices are communicatively coupled with each other and the USB3.2 host402 via one or more buses such as GEN2x2 buses Bus1 432, Bus2 434, andBus4 438; GEN2x1 buses such as Bus3 436, Bus5 440, and Bus7 444; GEN1x2buses Bus6 442, Bus9 450 and Bus11 454; and GEN1x1 buses Bus10 452, Bus8448, Bus12 456, Bus13 458, and Bus14 460.

In a USB3.2 network as shown in FIG. 4 above, it becomes a challengingtask to schedule concurrent transfers for one or more endpoints suchthat all the periodic endpoints are served within the ESIT with themaximum ESIT payload and no USB bus bandwidth is being exceeded.Further, data transfer between the USB3.2 host 402 and a USB peripheraldevice of the plurality of USB peripheral devices shown in FIG. 4 mayrequire multiple speed translations due to the fact that the buses thatconnect the USB3.2 host 402 and the USB peripheral device may supportdifferent transmission speeds. For example, for data transfers betweenthe USB3.2 host 402 and the USB peripheral device Dev1 406 may undergothree speed translations—GEN1x1 to GEN1X2 speed translation at the hubhub3 428, GEN1x2 to GEN2x1 speed translation at the hub hub2 426, andGEN2x1 to GEN2x2 speed translation at the hub hub1 404.

In addition to several speed translations for data transfer between theUSB host and the USB peripheral device, bandwidth limit for each USB busand a large number of combinations of scheduling order add to thecomplexity of scheduling optimization. However, using the method asdescribed herein, scheduling of data transfer may be optimized toimprove performance of the USB system without exceeding the busbandwidth usage of any of the buses. In other words, schedulingoptimization to improve performance of the USB system is achieved byidentifying which endpoints can be served concurrently.

In some embodiments, to identify whether two data transfer can bescheduled concurrently, a concept of bus bandwidth domain as describedherein may be applied. A bus bandwidth domain may be defined as a bus ora set of a plurality of USB buses that starts from either a USB hostroot port or a downstream port of a USB hub and ends at a USB peripheraldevice or an upstream port of a USB hub if the upstream port of the USBhub is operating at a different transmission speed from the downstreamport of the USB hub. The bus bandwidth domain concept is explained belowwith reference to FIG. 5.

FIG. 5 and FIG. 6 illustrate bandwidth domains, according to anexemplary embodiment of the present disclosure. The USB network shown inFIG. 5 is similar to USB networks as described above with reference toFIG. 1 through FIG. 3, and, therefore, is not described again. The USBnetwork as shown in FIG. 5 has three different bus bandwidth domains.The first bus bandwidth domain starts from a host root hub port (notshown) on a USB3.2 host 502 and ends at an upstream port (not shown) ona USB3.2 hub 504. Here, the USB3.2 hub 504 has one upstream port thatenables communication with the USB3.2 host 502, and two downstream ports(not shown) that enables communications of the USB3.2 hub 504 with afirst peripheral device 506 and a second peripheral device 508. Thetransmission speed supported at the USB hub 504's downstream port andthe upstream port is GEN2x1 and GEN2x2 respectively. Since thetransmission supported by the USB hub 504's downstream port and theupstream port are different, as described above, the first bandwidthdomain 510 that started at the USB host root port of the USB3.2 host 502would end at the upstream port of the USB hub 504.

Accordingly, a second bus bandwidth domain starts at the downstream portof the USB3.2 hub 504 and ends at the USB peripheral device 506, and athird bus bandwidth domain starts at the other downstream port of theUSB3.2 hub 504 and ends at the USB peripheral device 508. Table 1 belowshows the bandwidth domains and their corresponding buses in thebandwidth domain and the peripheral devices.

TABLE 1 Bandwidth Buses in the Bandwidth USB Peripherals in the domainDomain Bandwidth Domain BD1 Bus1 510 USB3.2 hub 504 BD2 Bus2 512 Dev1506 BD3 Bus3 514 Dev2 508

The USB network as shown in FIG. 6 is similar to similar to USB networksas described above with reference to FIG. 1 through FIG. 3, and,therefore, is not described again. However, a first USB peripheraldevice Dev1 606 in USB network shown in FIG. 6 is communicativelycoupled with a USB3.2 hub 604 via GEX2x2 bus Bus2 614 instead of GEN2x1bus. The USB network as shown in FIG. 6 has two different bus bandwidthdomains. The first bus bandwidth domain starts from a host root hub port(not shown) on a USB3.2 host 602 and ends at the first USB peripheraldevice Dev1 606 because an upstream port and a downstream port of theUSB3.2 hub 604 that provide communication between the USB3.2 host 602and the first USB peripheral device Dev1 606 are operating at the sametransmission speed, i.e., GEN2x2. For the USB network of FIG. 6, asecond bus bandwidth domain 514 starts at another downstream port of theUSB3.2 hub 604 and ends at the second USB peripheral device 608. Table 2below shows the bandwidth domains and their corresponding buses in thebandwidth domain and the peripheral devices for the USB network of FIG.6.

TABLE 2 Bandwidth Buses in the Bandwidth USB Peripherals in the domainDomain Bandwidth Domain BD1 Bus1 610, Bus2 614 USB3.2 hub 604, Dev1 606BD2 Bus3 612 Dev2 608

Bandwidth domains for a USB network as shown in FIG. 7 are summarized inTable 3 below. The USB network as shown in FIG. 7 is identical to theUSB network shown in FIG. 4. Accordingly, the USB network of FIG. 7 isnot being described again.

TABLE 3 Bandwidth Buses in the Bandwidth USB Peripherals in the domainDomain Bandwidth Domain BD1 Bus1 732, Bus2 734, Bus4 USB3.2 hub hub1704, 738 Dev7 718, Dev9 722 BD2 Bus3 736, Bus5 740, Bus7 USB3.2 hub hub2726, 744 Dev8 720, Dev10 724 BD3 Bus6 742, Bus9 748, USB3.2 hub hub3728, Bus11 752 Dev6 716, Dev4 712 BD4 Bus10 750 Dev5 714 BD5 Bus8 746,Bus12 754, USB3.2 hub hub4 730, Bus13 756, Bus14 758 Dev1 706, Dev2 708,Dev3 710

Detailed Description—Scheduling Optimization for a USB 3.2 NetworkTopology—4-Tuple Bandwidth Domains

As described above, USB3.2 standard supports four different transmissionspeeds—GEN2x2, GEN2x1, GEN1x2, and GEN1x1. Accordingly, it may berequired to support the following speed translations: from GEN2x2 toGEN2x1 or GEN1x2 or GEN1x1, from GEN2x1 to GEN1x2 or GEN1x1, and fromGEN1x2 to GEN1x1. Based on this, there are at most three speedtranslations along any USB path from a USB host to a USB peripheraldevice. By way of non-limiting example, there are at most four (4)bandwidth domains across a USB bus path between the USB host and any USBperipheral device. However, the maximum number of speed translations andthe maximum number of bandwidth domains across the USB bus path maydiffer according to the total number of different transmission speedssupported in the system.

In some embodiments, a 4-tuple of bandwidth domains for each USBperipheral device may be defined. The 4-tuple bandwidth domain comprisesall bandwidth domains across from the USB host to the USB peripheraldevice. The 4-tuple bandwidth domain may be described in the followingformat: [bandwidth domain 1, bandwidth domain 2, bandwidth domain 3,bandwidth domain 4].

In the 4-tuple bandwidth domain, “NA” may be designated if a specificbandwidth domain does not exist. The order of the 4-tuple may start fromthe bandwidth domain attached to the host root hub port, followed byother bandwidth domains along the USB path from the root hub port to theUSB peripheral device. When there are less than four bandwidth domainsalong the USB path from the USB host to the USB peripheral device, themissing bandwidth domains are filled with “NA”.

Table 4 below describes 4-tuple bandwidth domains for each USBperipheral device shown in FIG. 5 and based on Table 1 above.

USB Peripheral 4-tuple of Bandwidth Domains USB3.2 hub 504 [BD1, NA, NA,NA] Dev1 506 [BD1, BD2, NA, NA] Dev2 508 [BD1, BD3, NA, NA] Table 4

Table 5 below describes 4-tuple bandwidth domains for each USBperipheral device shown in FIG. 6 and based on Table 2 above.

TABLE 5 USB Peripheral 4-tuple of Bandwidth Domains USB3.2 hub 604 [BD1,NA, NA, NA] Dev1 606 [BD1, NA, NA, NA] Dev2 508 [BD1, BD2, NA, NA]

Table 6 below describes 4-tuple bandwidth domains for each USBperipheral device shown in FIG. 7 and based on Table 3 above.

TABLE 6 USB Peripheral 4-tuple of Bandwidth Domains USB3.2 hub hub1 704[BD1, NA, NA, NA] USB3.2 hub hub2 726 [BD1, BD2, NA, NA] USB3.2 hub hub3728 [BD1, BD2, BD3, NA] USB3.2 hub hub4 730 [BD1, BD2, BD3, BD5] Dev1706 [BD1, BD2, BD3, BD5] Dev2 708 [BD1, BD2, BD3, BD5] Dev3 710 [BD1,BD2, BD3, BD5] Dev4 712 [BD1, BD2, BD3, NA] Dev5 714 [BD1, BD2, BD3,BD5] Dev6 716 [BD1, BD2, BD3, NA] Dev7 718 [BD1, NA, NA, NA] Dev8 720[BD1, BD2, NA, NA] Dev9 722 [BD1, NA, NA, NA] Dev10 724 [BD1, BD2, NA,NA]

Detailed Description—Scheduling Optimization for a USB 3.2 NetworkTopology—Concurrency Score

As described above, to improve performance of the USB system and foroptimization of scheduling of data transfer, it may be required toidentify which endpoints may be scheduled for concurrent data transfer.A concurrency score may determine if the two endpoints may be scheduledfor simultaneous data transfer.

In some embodiments, by way of non-limiting example, a concurrency scoremay be determined as follows.

A concurrency score of value zero (0) may be assigned if the two USBperipheral devices are the same USB peripheral device. As describedabove, the USB peripheral device may be a USB device or a USB hub.

If the two USB peripheral devices are different, each element of a4-tuple of bandwidth domains of one USB peripheral device is comparedwith each element of a 4-tuple of bandwidth domains of another USBperipheral device. A sub concurrency score may be assigned forcomparison of the each element. While comparing the each element, a subconcurrency score of value 0 may be assigned if the two elements beingcompared are same, and a sub concurrency score of value 1 may beassigned if the two elements being compared are different. Accordingly,four sub concurrency scores, for example, sub_score_1, sub_score_2,sub_score_3, and sub_score_4 may be determined. Here, sub_score_1 maycorrespond with the comparison of the first element, i.e., “bandwidthdomain 1” field of the 4-tuple of the bandwidth domains. Similarlysub_score_2, sub_score_3, and sub_score_4 may correspond with thecomparison of the second, third, and fourth element, i.e., “bandwidthdomain 2,” “bandwidth domain 3,” and “bandwidth domain 4” fields of the4-tuple of the bandwidth domains.

By way of non-limiting example, a total concurrency score may bedetermined as a weighted score of the four sub concurrency scores usingthe equation below.

total concurrencyscore=sub_score_1*2⁴+sub_score_2*2³+sub_score_3*2²+sub_score_4*2¹+1

For example, to determine whether the USB device Dev3 710 and USB hubhub1 704 may be scheduled for concurrent data transfer can be determinedbased on a concurrency score calculated as shown above. A 4-tuple ofbandwidth domains for the USB device Dev3 710 is [BD1, BD2, BD3, BD5]according to Table 6 above. Similarly, a 4-tuple of bandwidth domainsfor the USB hub hub1 704 is [BD1, NA, NA, NA] according to Table 6above. Except “bandwidth domain 1” all other elements of the 4-tuple ofbandwidth domains are different for the USB device Dev3 710 and the USBhub hub1 704. Therefore, sub_score_1 may be assigned a value of zero (0)and sub_score_2, sub_score_3, and sub_score_4 each may be assigned avalue of one (1). A total concurrency score may therefore be 15calculated as (0*2⁴+1*2³+1*2²+1*2¹+1).

By way of non-limiting example, the total concurrency score may beassigned a value zero (0) if each element of a 4-tuple of bandwidthdomains of one USB peripheral device is same as the correspondingelement of a 4-tuple of bandwidth domains of another USB peripheraldevice, otherwise the total concurrency score may be assigned a value ofone (1). For example, a concurrency score of Dev2 708 with Dev3 710would be zero (0) because each element of a 4-tuple of bandwidth domainsof Dev2 708 is same as the corresponding element of a 4-tuple ofbandwidth domains of Dev3 710. Similarly, a concurrency score of Dev6716 with Dev8 720 would be one (1) because each element of a 4-tuple ofbandwidth domains of Dev6 716 is not same as the corresponding elementof a 4-tuple of bandwidth domains of Dev8 720.

Table 7 below lists concurrency score for each USB peripheral devicewith other USB peripheral device in the USB network of FIG. 7.

TABLE 7 Hub1 Hub2 Hub3 Hub4 dev1 Dev2 Dev3 Dev4 Dev5 Dev6 Dev7 Dev8 Dev9dev10 Hub1 0 9 13 15 15 15 15 13 15 13 1 9 1 9 Hub2 9 0 5 7 7 7 7 5 7 59 1 9 1 Hub3 13 5 0 3 3 3 3 1 3 1 13 5 13 5 Hub4 15 7 3 0 1 1 1 3 3 3 157 15 7 Dev1 15 7 3 1 0 1 1 3 3 3 15 7 15 7 Dev2 15 7 3 1 1 0 1 3 3 3 157 15 7 Dev3 15 7 3 1 1 1 0 3 3 3 15 7 15 7 Dev4 13 5 1 3 3 3 3 0 3 1 135 13 5 Dev5 15 7 3 3 3 3 3 3 0 3 15 7 15 7 Dev6 13 5 1 3 3 3 3 1 3 0 135 13 5 Dev7 1 9 13 15 15 15 15 13 15 13 0 9 1 9 Dev8 9 1 5 7 7 7 7 5 7 59 0 9 1 Dev9 1 9 13 15 15 15 15 13 15 13 1 9 0 9 Dev10 9 1 5 7 7 7 7 5 75 9 1 9 0

As another example, table 8 lists concurrency score for each USBperipheral device with other USB peripheral device in the USB network ofFIG. 7 in which the concurrency score is determined as a weighted scoreof the four sub concurrency scores using the below equation.

total concurrencyscore=sub_score_1*2³+sub_score_2*2²+sub_score_3*2¹+sub_score_4*1

TABLE 8 Hub1 Hub2 Hub3 Hub4 Dev1 Dev2 Dev3 Dev4 Dev5 Dev6 Dev7 Dev8 Dev9Dev10 Hub1 0 4 6 7 7 7 7 6 7 6 0 4 0 4 Hub2 4 0 2 3 3 3 3 2 3 2 4 0 4 0Hub3 6 2 0 1 1 1 1 0 1 0 6 2 6 2 Hub4 7 3 1 0 0 0 0 1 1 1 7 3 7 3 Dev1 73 1 0 0 0 0 1 1 1 7 3 7 3 Dev2 7 3 1 0 0 0 0 1 1 1 7 3 7 3 Dev3 7 3 1 00 0 0 1 1 1 7 3 7 3 Dev4 6 2 0 1 1 1 1 0 1 0 6 2 6 2 Dev5 7 3 1 1 1 1 11 0 1 7 3 7 3 Dev6 6 2 0 1 1 1 1 0 1 0 6 2 6 2 Dev7 0 4 6 7 7 7 7 6 7 60 4 0 4 Dev8 4 0 2 3 3 3 3 2 3 2 4 0 4 0 Dev9 0 4 6 7 7 7 7 6 7 6 0 4 04 Dev10 4 0 2 3 3 3 3 2 3 2 4 0 4 0

In some embodiments, one or more concurrency scores for each USBperipheral device with reference to one or more other USB peripheraldevices in the USB network may be pre-calculated and stored in a memoryof the USB host. The one or more concurrency scores for each USBperipheral device may be updated when a new USB peripheral device joinsor an existing USB peripheral device leaves the USB network. In someembodiments, the one or more concurrency scores for each USB peripheraldevices may be stored using reduced memory because as can be seen fromthe Table 7 above, the concurrency score table is symmetric and theentries along the diagonal direction from the top left to bottom rightare all zero (0).

In some embodiments, the concurrency score may be determined by the USBhost as required during scheduling of the data transfer using any of theabove exemplary methods or other methods.

As described above, the basic requirement for periodic scheduling isthat all the configured periodic endpoints are served based on theirESIT and maximum ESIT payloads. In some embodiments, this may beachieved by creating a sorted list of all the periodic endpoints basedon their service intervals. An endpoint with the smallest serviceinterval may be scheduled first for data transfer, and an endpoint withthe largest service interval may be scheduled last for data transfer.

In accordance with some embodiments, FIG. 8 illustrates an exampleperiodic endpoint list sorted based on ESIT value of a plurality ofendpoints of a plurality of USB peripheral devices of FIG. 7. Aplurality of endpoints 802, 804, 806, 808, 810, 812, 814, 816, 818 and820 of the plurality of USB peripheral devices are sorted based on ESITvalue. Endpoints with smallest service interval time are scheduled fordata transfer ahead of the other endpoints with larger service intervaltime. For example, endpoints 802, 804, 806, and 808 each with a serviceinterval time of zero (0) are scheduled ahead of endpoints 810, 812, and814. Similarly, endpoints 816, 818, and 820 with a service interval timeof two (2) are scheduled for the transmission last. The endpoints shownin FIG. 8 are from the USB network shown in FIG. 7.

In some embodiments, the periodic endpoint list of FIG. 8 may beoptimized using the concurrency score calculated or determined asdescribed above. The periodic endpoint list of FIG. 8 is furtheradjusted based on the concurrency score of the plurality of the USBperipheral devices as shown in FIG. 9. The endpoints of the same serviceinterval are placed one after another in the list if they are from USBperipherals of the highest concurrency score. For example, in FIG. 8,endpoint EP1 of Dev9 722 is scheduled for data transfer followed by EP2of Dev9 722 followed by EP1 of Dev1 706 followed by EP2 of Dev1 706. Aconcurrency score of EP1 of Dev9 722 with reference to EP2 of Dev9 722is zero based on Table 7 above. However, concurrency score of EP2 ofDev9 722 with reference to EP1 of Dev1 706 is fifteen (15). Therefore,the EP1 of Dev1 706 is scheduled ahead of EP2 of Dev9 722 as shown inFIG. 9. Though, only concurrency score of the first selected endpoint,i.e., EP2 of Dev9 722 is compared with its concurrency score withrespect to EP1 of Dev9 722 and EP1 of Dev1 706 for brevity, theconcurrency score may be compared against all remaining endpoints havinga similar value of ESIT to determine an endpoint for each position.Based on the sorting procedure as described above, EP1 of Dev8 720 isscheduled ahead of EP1 of Dev3 710 as shown in FIG. 9 because aconcurrency score of EP1 of Dev2 708 with respect to EP1 of Dev8 720 is7, which is higher than a concurrency score of EP1 of Dev2 708 withrespect to EP1 of Dev3 710 that is 1 according to Table 7. An order ofendpoints based on service interval time as shown in FIG. 8 is 802, 804,806, 808, 810, 812, 814, 816, 818, and 820 when sorted again based onthe concurrency score as shown in FIG. 9 is 902, 906, 904, 908, 910,914, 912, 916, 920 and 918. Where the endpoint 802 corresponds with theendpoint 902, the endpoint 806 corresponds with the endpoint 906, and soon. The endpoints shown in FIG. 9 are from the USB network shown in FIG.7. Further, the ordering of endpoints in FIG. 8 and FIG. 9 correspondsto scheduling for a micro frame.

Sorting of the endpoints as described above may generate a list ofdifferent order of endpoints if a different endpoint is selected to betransmitted first, which may or may not allow concurrent transfer forsome of the endpoints. Accordingly, multiple iterations may be executedto determine a sorted list of endpoints based on the ESIT andconcurrency score, and the sorted list in which USB bus utilization maybe maximized may be selected.

FIG. 10 illustrates an order of scheduling tokens, according to anexemplary embodiment of the present disclosure. As a result of the hostperiodic scheduling a list of scheduling tokens for each micro frame aregenerated. In some embodiments, by way of non-limiting example, thescheduling token may specify information including a total number ofpackets, an endpoint of a USB peripheral device, and an order in whichthey are to be transferred or communicated. As described above withreference to FIG. 8, once the list of periodic endpoints is created, theperiodic scheduling process may invoke a sub-process known as endpointfitting to generate the scheduling tokens for each micro frame.Accordingly, the endpoint fitting sub-process may generate schedulingtokens according to which for a micro frame #0 1068 scheduling tokens1002, 1004, 1006, 1008, 1010, 1012, 1014, 1016, and 1018 are to betransmitted in the order specified here. Similarly, for a micro frame #11070 scheduling tokens 1020, 1022, 1024, and 1026 are to be transmittedin the order specified here. Similarly, scheduling tokens may begenerated for a micro frame #2, a micro frame #3, and a micro frame #4.

FIG. 11 illustrates an order of scheduling tokens adjusted based onconcurrent scores, according to an exemplary embodiments of the presentdisclosure. As described above with reference to FIG. 9 to sort theendpoints using concurrency score according to Table 7, schedulingtokens are rearranged based on the concurrency scores for each microframe. As shown in FIG. 11, scheduling tokens for a micro frame #0 1168are rearranged as 1102, 1104, 1106, 1108, 1112, 1110, 1118, 1116, and1114. However, for a micro frame #1, rearrangement based on theconcurrency score does not change an order of the scheduling tokens.

Detailed Description—Scheduling Optimization for a USB 3.2 NetworkTopology—Determining Bandwidth

As described above, another requirement is the no USB bus bandwidthlimit should be exceeded. Accordingly, it is required that the availablebandwidth for the USB bus be shared among a number of packets to becommunicated with a plurality of USB peripheral devices based on thesize of the packets. As described above, USB buses of USB3.2 standardmay support four (4) different bandwidths and there may be three (3)different speed translations along a USB path from a USB host to a USBperipheral device. Therefore, bandwidth determination may becomechallenging. However, the bandwidth for IN transfer and OUT transfer maybe determined as described herein.

Following useful terms are defined to help a person skilled in the artto practice the embodiments described herein.

STF: speed translation factor=fast bus speed divided by slow bus speed.

STF₁₂, STF_(BD13), STF_(BD14), STF_(BD23), STF_(BD34) are speedtranslation factors between BD1 and BD2, BD1 and BD3, BD1 and BD4, BD2and BD3, BD3 and BD4, respectively.

ISTF: inverse speed translation factor=slow bus speed divided by fastbus speed.

ISTF_(BD12),ISTF_(BD13),ISTF_(BD14),ISTF_(BD23),ISTF_(BD24) are inversespeed translation factors between BD 1 and 2, BD 1 and 3, BD 1 and 4, BD2 and 3, BD 3 and 4, respectively.

Hub_(delay): delay caused by USB hubs.

total_(numberofhub): total number of hubs between the root hub port andthe USB peripheral device.

Number_(ofhubBD234) number of hubs between the first speed translationhub and the USB peripheral device.

Number_(ofhubBD1) number of hubs between the first BD and the second BD.

Speed_(BD1), Speed_(BD2), Speed_(BD3), Speed_(BD4): bus speed of thefirst, second, third and fourth BDs respectively.

Bandwidth is defined as the number of bytes that can be received or sentduring a specific period of time.

Used bandwidth is defined as the number of bytes that could have beenreceived or sent from the current micro frame start to present time.Used_(bandwidthBD1), Used_(bandwidthBD2), Used_(bandwidthBD3),Used_(bandwidthBD4) are used bandwidths of BD1, BD2, BD3 and BD4,respectively.

Total bandwidth is defined as the number of bytes that could have beenreceived or sent from the beginning to the end of the micro frame.

Total_(bandwidthBD1), Total_(bandwidthBD2), Total_(bandwidthBD3),Total_(bandwidthBD4) are Total available bandwidths of BD1, BD2, BD3 andBD4, respectively.

To simplify the description, it is being assumed that the path from theroot hub port to the USB peripheral devices of the EP always crossesfour bandwidth domains.

To apply the formula to the case where the path from the root hub portto the USB peripheral devices of the EP crosses one bandwidth domain,two bandwidth domains, or three bandwidth domains, zero bandwidth may beassigned to the missing bandwidth domains.

Total available bandwidth is defined as the total number of bytes thatcan be received or sent from present time to the end of the micro frame.

Remaining bandwidth=total available bandwidth−used bandwidth.

For successful scheduling for a micro frame, it may be required thatremaining bandwidths of all BDs are greater or equal to zero. Forsuccessful scheduling for an EP, it may be required successfulscheduling for all micro frames for the EP. For successful periodicscheduling, it may be required successful scheduling for all EPs.Bandwidth calculations for OUT transfer and IN transfer are describedbelow in detail.

Bandwidth calculations for OUT transfers:

The transmit (TX) throughput of the USB network is restricted by theslowest bus. In some embodiments, by way of non-limiting example, abandwidth required for an OUT endpoint to transmit N bytes may becalculated using following steps.

In step 1, speed of the OUT endpoint may be obtained.

In step 2, speed of a first bus bandwidth domain may be obtained.

In step 3, speed translation factor between the first bus bandwidthdomain and the bus bandwidth domain where the OUT endpoint is locatedmay be determined.

In step 4, used bandwidth for the first bus bandwidth domain may beobtained using the following equation.

Used_Bandwidth_(BD1)=Used_Bandwidth_(BD1)(old)+N*STF+Speed_(BD1)*hub_delay*total_number_of_hubs

When there is no other endpoint being scheduled for concurrent transfer,then used bandwidth for the first bus bandwidth domain may only beconsidered in the calculations.

In some embodiments, one or more transmit engines may be used totransmit data from OUT endpoints. Status of the one or more transmit(TX) engines may be maintained by periodically checking size of thenumber of TX engines and/or completion time for packets scheduled to betransmitted by the one or more TX engines. By way of non-limitingexamples, the number of bytes that may have been transferred on thefirst bus bandwidth domain may be determined for a micro frame since thebeginning of the micro frame to the completion time. For each microframe, TX completion list for each TX engine may be initialized withzero (0).

In some embodiments, if there are enough buffers in a USB hub wherespeed translation may occur, no flow control may be applied on the datatransfer at the upstream port of the USB hub.

In some embodiments, when the EP is being concurrently scheduled fordata transfer with other endpoint(s), the used bandwidth for transfer ofN bytes may be calculated as follows.

In step 1, find all bus bandwidth domains or a 4-tuple of bus bandwidthdomains of a USB peripheral device as described above.

In step 2, obtain the used bandwidth for all bus bandwidth domains orfor each element of the 4-tuple of bus bandwidth domains of the USBperipheral device.

In step 3, find an entry in the TX completion list that has the earliestcompletion time TX_(Ci). In other words, a TX engine with less number ofbytes pending to transmit may be determined.

In step 4, start time for transmission TX_(start) may be determinedaccording to TX_(start)=max (TX_(Ci), Used_Bandwidth_BD1 (old),Used_Bandwidth_BD2 (old)*STF_(BD12), Used_Bandwidth_BD3(old)*STF_(BD13), Used_Bandwidth_BD4 (old)*STF_(BD14)).

In step 5, the used bandwidth for all bus bandwidth domains may beupdated according to:

Used_Bandwidth_BD1 (adjust)=TX_(start).

Used_Bandwidth_BD2 (old)=TX_(start)*ISTF_(BD12).

Used_Bandwidth_BD3 (old)=TX_(start)*ISTF_(BD13).

Used_Bandwidth_BD4 (old)=TX_(start)*ISTF_(BD14).

In step 6, the used bandwidth for all bus bandwidth domains may beupdated according to:

Used_Bandwidth_BD1=Used_Bandwidth_BD1 (old)+N.

Used_Bandwidth_BD2=Used_Bandwidth_BD2(old)+N+Speed_(BD2)*hub_delay*number_of_hubs_(BD12)

Used_Bandwidth_BD3=Used_Bandwidth_BD3(old)+N+Speed_(BD3)*hub_delay*number_of_hubs_(BD13)

Used_Bandwidth_BD4=Used_Bandwidth_BD4(old)+N+Speed_(BD4)*hub_delay*number_of_hubs_(BD14)

In step 7, an entry of the earliest completion time in the TX completionlist may be replaced with Used_Bandwidth_BD1 as calculated above.

In some embodiments, a total number of packets an OUT endpoint may sendwith the available bandwidth may be determined as follows.

In step 1, find all bus bandwidth domains or a 4-tuple of bus bandwidthdomains of a USB peripheral device as described above.

In step 2, obtain the used bandwidth for all bus bandwidth domains orfor each element of the 4-tuple of bus bandwidth domains of the USBperipheral device.

In step 3, find an entry in the TX completion list that has the earliestcompletion time TX_(Ci). In other words, a TX engine with less number ofbytes pending to transmit may be determined.

In step 4, start time for transmission TX_(start) may be determinedaccording to TX_(start)=max (TX_(Ci), Used_Bandwidth_BD1 (old),Used_Bandwidth_BD2 (old)*STF_(BD12), Used_Bandwidth_BD3(old)*STF_(BD13), Used_Bandwidth_BD4 (old)*STF_(BD14)).

In step 5, used bandwidths for a primary bus, a first secondary, asecond secondary bus, and a third secondary bus may be determined asfollows:

Used_Bandwidth_BD1=TX_(start).

Used_Bandwidth_BD2=TX_(start)*ISTF_(BD12).

Used_Bandwidth_BD3=TX_(start)*ISTF_(BD13).

Used_Bandwidth_BD4=TX_(start)*ISTF_(BD14).

In step 6, total number of packets that can be sent out may bedetermined astotal_number_of_packets=(Total_Bandwidth_BD1−Used_Bandwidth_BD1)/Maximum_Packet_Size.

In some embodiments, similar to the TX completion list, a RX completionlist may be maintained, and a total number of packets that may bereceived may be determined as described above.

Detailed Description—Scheduling Optimization for a USB 3.2 NetworkTopology—an Example Method

FIG. 12 illustrates a flow diagram of USB host periodic scheduling,according to an exemplary embodiment of the present disclosure. Themethod steps described here may be performed by one or more processorsof a USB host. At step 1202, a subset of a plurality of endpoints forcommunication during a communication frame may be sorted based on avalue of service interval assigned to each endpoint of the subset of theplurality of endpoints. The communication frame as described above maybe a micro frame. The plurality of endpoints may include one or moreendpoints of a first peripheral device and one or more endpoints of asecond peripheral device.

At step 1204, the sorted subset of the plurality of endpoints may besorted again based on a concurrency score of the first peripheral devicewith the second peripheral device. The sorting based on concurrencyscore may optimize scheduling as described above. To determineconcurrency score, one or more bus bandwidth domains and one or morebuses between a host device and the first peripheral device and the hostdevice and the second peripheral device may be identified. The one ormore bus bandwidth domains between the host device and the firstperipheral device and the host device and the second peripheral devicemay be ordered based on proximity of the one or more bus bandwidthdomains from the host device. Subsequently, the ordered one or more busbandwidth domains between the host device and the first peripheraldevice may be compared with the ordered one or more bus bandwidthdomains between the host device and the second peripheral device todetermine the concurrency score of the first peripheral device with thesecond peripheral device. In other words, the ordered one or more busbandwidth domains form n-tuple of bandwidth domains, where n representsa total number of unique data speeds supported by the USB system.

In some embodiments, for the comparing the ordered one or more busbandwidth domains, each element of a first n-tuple of bandwidth domainsbetween the host device and the first peripheral device may be comparedwith an similarly indexed element of a second n-tuple of bandwidthdomains between the host device and the second peripheral device. Inresponse to the comparison showing the compared at least one element ofthe first n-tuple of bandwidth domains with the similarly indexedelement of the second n-tuple of bandwidth domains being different, theconcurrency score of the first peripheral device with the secondperipheral device be assigned a value of one (1) indicating the firstperipheral device and the second peripheral device can be concurrentlyserved.

In some embodiments, for the comparing the ordered one or more busbandwidth domains, each element of a first n-tuple of bandwidth domainsbetween the host device and the first peripheral device may be comparedwith an similarly indexed element of a second n-tuple of bandwidthdomains between the host device and the second peripheral device. Inresponse to the comparison showing the compared element of the firstn-tuple of bandwidth domains with the similarly indexed element of thesecond n-tuple of bandwidth domains being different, a weightedsub-score may be generated for the compared element of the first n-tupleof bandwidth domains. The concurrency score of the first peripheraldevice with the second peripheral device may be generated based on theweighted sub-score for the compared element of the first n-tuple ofbandwidth domains with the similarly indexed element of the secondn-tuple of bandwidth domains being different.

In some embodiments, the generated concurrency score may be a firstpreconfigured value, a second preconfigured value, or a value in betweenthe first preconfigured value and the second preconfigured value. Thefirst preconfigured value may be smaller than the second preconfiguredvalue.

In some embodiments, the generated concurrency score above apreconfigured threshold value may indicate the first peripheral deviceand the second peripheral device can be concurrently served.

At step 1206, available bandwidth for communication with the eachendpoint of the subset of the plurality of endpoints may be determined.For determining the available bandwidth, required bandwidth forcommunicating a plurality of packets based on a transmission speedtranslation factor between a bandwidth domain of a host device andbandwidth domain of the first peripheral device may be determined. Thetransmission speed translation factor may be determined by dividing alarger speed of the bandwidth domain of the host device or theperipheral device by a smaller speed of the bandwidth domain of the hostdevice or the first peripheral device. Available bandwidth may bedetermined as a difference of the required bandwidth and the usedbandwidth, which may be determined based on transmission speedtranslation factors of one or more bandwidth domains between a hostdevice and the first peripheral device.

At step 1208, based on the determined available bandwidth, a number ofpackets to be communicated with the each endpoint of the subset of theplurality of endpoints may be determined. As described above, a totalnumber of packets that can be transferred may be determined based on theavailable bandwidth and maximum packet size.

At step 1210, a scheduling table for communicating the number of packetswith the each endpoint of the subset of the plurality of endpoints basedon the concurrency score of the first peripheral device with the secondperipheral device may be generated. The generated scheduling table mayinclude the number of packets to be communicated with the each endpointof the subset of the plurality of endpoints and an order ofcommunication of the number of packets to be communicated with the eachendpoint of the subset of the plurality of endpoints.

As described above, various embodiments as described herein may be usedto optimize host periodic scheduling in any network including a USBnetwork to improve USB bandwidth utilization. Various embodimentsdescribed herein are not limited to USB3.2 standard but can be easilyextended for future USB standards and other similar areas ofapplications.

Detailed Description—Technology Support from Data/Instructions toProcessors/Programs

Data and Information. While ‘data’ and ‘information’ often are usedinterchangeably (e.g., ‘data processing’ and ‘information processing’),the term ‘datum’ (plural ‘data’) typically signifies a representation ofthe value of a measurement of a physical quantity (e.g., the current ina wire), or the answer to a question (e.g., “yes” or “no”), while theterm ‘information’ typically signifies a structured set of data (oftentimes signified by ‘data structure’). A specified data structure is usedto structure an electronic device to be used as a specific machine as anarticle of manufacture (see In re Lowry, 32 F.3d 1579 [CAFC, 1994]).Data and information are physical, for example binary data (a ‘bit’,usually signified with ‘0’ and ‘1’) enabled with two different levels ofvoltage in a circuit. For example, data can be enabled as an electrical,magnetic, optical or acoustical signal; a quantum state such as spinthat enables a ‘qubit’; or a physical state of an atom or molecule. Allsuch data and information, when enabled, are stored, accessed,transferred, combined, compared, or otherwise acted upon, actions thatrequire energy.

As used herein, the term ‘process’ signifies an unnatural sequence ofphysical actions and/or transformations (both also referred to as‘operations’ or ‘steps’) to produce at least one result. The actions andtransformations are technical applications of one or more natural lawsof science or unnatural laws of technology. The actions andtransformations often change the physical state of a machine, ofstructures of data and information, or of a composition of matter. Twoor more actions can occur at about the same time, or one action canoccur before or after another action, if they produce the same result. Adescription of the physical actions and/or transformations that comprisea process are often signified with a set of gerund phrases (or theirsemantic equivalents) that are typically preceded with the signifier‘the steps of’ (e.g., “a process comprising the steps of measuring,transforming, partitioning and then distributing . . . ”). Thesignifiers ‘algorithm’, ‘method’, ‘procedure’, ‘(sub)routine’,‘protocol’, ‘recipe’, and ‘technique’ often are used interchangeablywith ‘process’, and 35 U.S.C. 100 defines a “method” as one type ofprocess that is, by statutory law, always patentable under 35 U.S.C.101. Many forms of knowledge, learning, skills and styles are authored,structured, and enabled—objectively—as processes—e.g., knowledge andlearning as functions in knowledge programming languages. As usedherein, the term ‘rule’ signifies a process with at least oneconditional test (signified, e.g., by ‘IF test THEN process’). As usedherein, the term ‘thread’ signifies a sequence of operations orinstructions that comprise a subset of an entire process. A process canbe partitioned into multiple threads that can be used at or about at thesame time.

As used herein, the term ‘component’ (also signified by ‘part’, andtypically signified by ‘element’ when described in a patent text ordiagram) signifies a physical object that is used to enable a process incombination with other components. For example, electronic componentsare used in processes that affect the physical state of one or moreelectromagnetic or quantum particles/waves (e.g., electrons, photons) orquasiparticles (e.g., electron holes, phonons, magnetic domains) andtheir associated fields or signals. Electronic components have at leasttwo connection points to which are attached ‘leads’, typically aconductive wire or an optical fiber, with one end attached to thecomponent and the other end attached to another component, typically aspart of a circuit with current flows. There are at least three types ofelectrical components: passive, active and electromechanical. Passiveelectronic components typically do not introduce energy into acircuit—such components include resistors, memristors, capacitors,magnetic inductors, crystals, Josephson junctions, transducers, sensors,antennas, waveguides, etc. Active electronic components require a sourceof energy and can inject energy into a circuit—such components includesemiconductors (e.g., diodes, transistors, optoelectronic devices),vacuum tubes, batteries, power supplies, displays (e.g., LEDs, LCDs,lamps, CRTs, plasma displays). Electromechanical components affectcurrent flow using mechanical forces and structures—such componentsinclude switches, relays, protection devices (e.g., fuses, circuitbreakers), heat sinks, fans, cables, wires, terminals, connectors andprinted circuit boards. As used herein, the term ‘netlist’ is aspecification of the components comprising an electric circuit, andelectrical connections between the components. The programming languagefor the SPICE circuit simulation program is often used to specify anetlist. In the context of circuit design, the term ‘instance’ signifieseach time a component is specified in a netlist.

One of the most important components as goods in commerce is theintegrated circuit, and its res of abstractions. As used herein, theterm ‘integrated circuit’ signifies a set of connected electroniccomponents on a small substrate (thus the use of the signifier ‘chip’)of semiconductor material, such as silicon or gallium arsenide, withcomponents fabricated on one or more layers. Other signifiers for‘integrated circuit’ include ‘monolithic integrated circuit’, ‘IC’,‘chip’, ‘microchip’ and ‘System on Chip’ (‘SoC’). Examples of types ofintegrated circuits include gate/logic arrays, processors, memories,interface chips, power controllers, and operational amplifiers. The term‘cell’ as used in electronic circuit design signifies a specification ofone or more components, for example, a set of transistors that areconnected to function as a logic gate. Cells are usually stored in adatabase, to be accessed by circuit designers and design processes.

As used herein, the term ‘module’ signifies a tangible structure foracting on data and information. For example, the term ‘module’ cansignify a process that transforms data and information, for example, aprocess comprising a computer program. The term ‘module’ also cansignify one or more interconnected electronic components, such asdigital logic devices. A process comprising a module, if specified in aprogramming language, such as System C or Verilog, also can betransformed into a specification for a structure of electroniccomponents that transform data and information that produce the sameresult as the process. This last sentence follows from a modifiedChurch-Turing thesis, which is simply expressed as “Whatever can betransformed by a (patentable) process and a processor, can betransformed by a (patentable) equivalent set of modules,” as opposed tothe doublethink of deleting only one of the “(patentable)”.

A module is permanently structured (e.g., circuits with unalterableconnections), temporarily structured (e.g., circuits or processes thatare alterable with sets of data), or a combination of the two forms ofstructuring. Permanently structured modules can be manufactured, forexample, using Application Specific Integrated Circuits (‘ASICs’) suchas Arithmetic Logic Units (‘ALUs’), Programmable Logic Arrays (‘PLAs’),or Read Only Memories (‘ROMs’), all of which are typically structuredduring manufacturing. For example, a permanently structured module cancomprise an integrated circuit. Temporarily structured modules can bemanufactured, for example, using Field Programmable Gate Arrays(FPGAs—for example, sold by Xilink or Intel's Altera), Random AccessMemories (RAMs) or microprocessors. For example, data and information istransformed using data as an address in RAM or ROM memory that storesoutput data and information. One can embed temporarily structuredmodules in permanently structured modules (for example, a FPGA embeddedinto an ASIC).

Modules that are temporarily structured can be structured duringmultiple time periods. For example, a processor comprising one or moremodules has its modules first structured by a manufacturer at a factoryand then further structured by a user when used in commerce. Theprocessor can comprise a set of one or more modules during a first timeperiod, and then be restructured to comprise a different set of one ormodules during a second time period. The decision to manufacture orimplement a module in a permanently structured form, in a temporarilystructured form, or in a combination of the two forms, depends on issuesof commerce such as cost, time considerations, resource constraints,tariffs, maintenance needs, national intellectual property laws, and/orspecific design goals. How a module is used is mostly independent of thephysical form in which it is manufactured or enabled. This last sentencealso follows from the modified Church-Turing thesis.

As used herein, the term ‘processor’ signifies a tangible data andinformation processing machine for use in commerce that physicallytransforms, transfers, and/or transmits data and information, using atleast one process. A processor consists of one or more modules (e.g., acentral processing unit, ‘CPU’; an input/output (‘I/O’) controller, amemory controller, a network controller, and other modules). The term‘processor’ can signify one or more processors, or one or moreprocessors with multiple computational cores/CPUs, specializedprocessors (for example, graphics processors or signal processors), andtheir combinations. Where two or more processors interact, one or moreof the processors can be remotely located. Where the term ‘processor’ isused in another context, such as a ‘chemical processor’, it will besignified and defined in that context.

The processor can comprise, for example, digital logic circuitry (forexample, a binary logic gate), and/or analog circuitry (for example, anoperational amplifier). The processor also can use optical signalprocessing, DNA transformations or quantum operations, microfluidiclogic processing, or a combination of technologies, such as anoptoelectronic processor. For data and information structured withbinary data, any processor that can transform data and information usingthe AND, OR and NOT logical operations (and their derivatives, such asthe NAND, NOR, and XOR operations) also can transform data andinformation using any function of Boolean logic. A processor such as ananalog processor, such as an artificial neural network, also cantransform data and information. No scientific evidence exists that anyof these technological processors are processing, storing and retrievingdata and information, using any process or structure equivalent to thebioelectric structures and processes of the human brain.

The one or more processors also can use a process in a ‘cloud computing’environment, where time and resources of multiple remote computers areshared by multiple users or processors communicating with the computers.For example, a group of processors can use at least one processavailable at a distributed or remote system, these processors using acommunications network (e.g., the Internet, or an Ethernet) and usingone or more specified interfaces (e.g., an application program interface(‘API’) that signifies functions and data structures to communicate withthe remote process).

As used herein, the term ‘computer’ and ‘computer system’ (furtherdefined below) includes at least one processor that, for example,performs operations on data and information such as (but not limited to)the AND, OR and NOT logical operations using electronic gates that cancomprise transistors, with the addition of memory (for example, memorystructured with flip-flops using the NOT-AND or NOT-OR operation). Sucha processor is Turing-complete and computationally universal. A computercan comprise a simple structure, for example, comprising an I/O module,a CPU, and a memory that performs, for example, the process of inputtinga signal, transforming the signal, and outputting the signal with nohuman intervention.

As used herein, the term ‘programming language’ signifies a structuredgrammar for specifying sets of operations and data for use by modules,processors and computers. Programming languages include assemblerinstructions, instruction-set-architecture instructions, machineinstructions, machine dependent instructions, microcode, firmwareinstructions, state-setting data, or either source code or object codewritten in any combination of one or more higher level languages, forexample, the C programming language and similar general programminglanguages (such as Fortran, Basic, Javascript, PHP, Python, C++),knowledge programming languages (such as Lisp, Smalltalk, Prolog, orCycL), electronic structure programming languages (such as VHDL,Verilog, SPICE or SystemC), text programming languages (such as SGML,HTML, or XML), or audiovisual programming languages (such as SVG,MathML, X3D/VRML, or MIDI), and any future equivalent programminglanguages. As used herein, the term ‘source code’ signifies a set ofinstructions and data specified in text form using a programminglanguage. A large amount of source code for use in enabling any of theclaimed inventions is available on the Internet, such as from a sourcecode library such as Github.

As used herein, the term ‘program’ (also referred to as an ‘applicationprogram’) signifies one or more processes and data structures thatstructure a module, processor or computer to be used as a “specificmachine” (see In re Alappat, 33 F3d 1526 [CAFC, 1991]). One use of aprogram is to structure one or more computers, for example, standalone,client or server computers, or one or more modules, or systems of one ormore such computers or modules. As used herein, the term ‘computerapplication’ signifies a program that enables a specific use, forexample, to enable text processing operations, or to encrypt a set ofdata. As used herein, the term ‘firmware’ signifies a type of programthat typically structures a processor or a computer, where the firmwareis smaller in size than a typical application program, and is typicallynot very accessible to or modifiable by the user of a computer. Computerprograms and firmware are often specified using source code written in aprogramming language, such as C. Modules, circuits, processors,programs, and computers can be specified at multiple levels ofabstraction, for example, using the SystemC programming language, andhave value as products in commerce as taxable goods under the UniformCommercial Code (see U.C.C. Article 2, Part 1).

A program is transferred into one or more memories of the computer orcomputer system from a data and information device or storage system. Acomputer system typically has a device for reading storage media that isused to transfer the program, and/or has an interface device thatreceives the program over a network. This process is discussed in theGeneral Computer Explanation section.

Detailed Description—Technology Support General Computer Explanation

FIGS. 14A and 14B are abstract diagrams of a computer system suitablefor enabling embodiments of the claimed inventions.

In FIG. 14A, the structure of computer system 1410 typically includes atleast one computer 1414 which communicates with peripheral devices viabus subsystem 1412. Typically, the computer includes a processor (e.g.,a microprocessor, graphics processing unit, or digital signalprocessor), or its electronic processing equivalents, such as anApplication Specific Integrated Circuit (‘ASIC’) or Field ProgrammableGate Array (‘FPGA’). Typically, peripheral devices include a storagesubsystem 1424, comprising a memory subsystem 1426 and a file storagesubsystem 1428, user interface input devices 1422, user interface outputdevices 1420, and/or a network interface subsystem 1416. The input andoutput devices enable direct and remote user interaction with computersystem 1410. The computer system enables significant post-processactivity using at least one output device and/or the network interfacesubsystem.

The computer system can be structured as a server, a client, aworkstation, a mainframe, a personal computer (PC), a tablet PC, aset-top box (STB), a personal digital assistant (PDA), a cellulartelephone, a smartphone, a web appliance, a rack-mounted ‘blade’, akiosk, a television, a game station, a network router, switch or bridge,or any data processing machine with instructions that specify actions tobe taken by that machine. The term ‘server’, as used herein, refers to acomputer or processor that typically performs processes for, and sendsdata and information to, another computer or processor.

A computer system typically is structured, in part, with at least oneoperating system program, such as Microsoft's Windows, SunMicrosystems's Solaris, Apple Computer's MacOs and iOS, Google'sAndroid, Linux and/or Unix. The computer system typically includes aBasic Input/Output System (BIOS) and processor firmware. The operatingsystem, BIOS and firmware are used by the processor to structure andcontrol any subsystems and interfaces connected to the processor.Typical processors that enable these operating systems include: thePentium, Itanium and Xeon processors from Intel; the Opteron and Athlonprocessors from Advanced Micro Devices; the Graviton processor fromAmazon; the POWER processor from IBM; the SPARC processor from Oracle;and the ARM processor from ARM Holdings.

The claimed inventions and their embodiments are limited neither to anelectronic digital logic computer structured with programs nor to anelectronically programmable device. For example, the claimed inventionscan use an optical computer, a quantum computer, an analog computer, orthe like. Further, where only a single computer system or a singlemachine is signified, the use of a singular form of such terms also cansignify any structure of computer systems or machines that individuallyor jointly use processes. Due to the ever-changing nature of computersand networks, the description of computer system 1410 depicted in FIG.14A is intended only as an example. Many other structures of computersystem 1410 have more or less components than the computer systemdepicted in FIG. 14A.

Network interface subsystem 1416 provides an interface to outsidenetworks, including an interface to communication network 1418, and iscoupled via communication network 1418 to corresponding interfacedevices in other computer systems or machines. Communication network1418 can comprise many interconnected computer systems, machines andphysical communication connections (signified by ‘links’). Thesecommunication links can be wireline links, optical links, wireless links(e.g., using the WiFi or Bluetooth protocols), or any other physicaldevices for communication of information. Communication network 1418 canbe any suitable computer network, for example a wide area network suchas the Internet, and/or a local-to-wide area network such as Ethernet.The communication network is wired and/or wireless, and manycommunication networks use encryption and decryption processes, such asis available with a virtual private network. The communication networkuses one or more communications interfaces, which receive data from, andtransmit data to, other systems. Embodiments of communicationsinterfaces typically include an Ethernet card, a modem (e.g., telephone,satellite, cable, or ISDN), (asynchronous) digital subscriber line (DSL)unit, Firewire interface, USB interface, and the like. Communicationalgorithms (‘protocols’) can be specified using one or communicationlanguages, such as HTTP, TCP/IP, RTP/RTSP, IPX and/or UDP.

User interface input devices 1422 can include an alphanumeric keyboard,a keypad, pointing devices such as a mouse, trackball, toggle switch,touchpad, stylus, a graphics tablet, an optical scanner such as a barcode reader, touchscreen electronics for a display device, audio inputdevices such as voice recognition systems or microphones, eye-gazerecognition, brainwave pattern recognition, optical characterrecognition systems, and other types of input devices. Such devices areconnected by wire or wirelessly to a computer system. Typically, theterm ‘input device’ signifies all possible types of devices andprocesses to transfer data and information into computer system 1410 oronto communication network 1418. User interface input devices typicallyenable a user to select objects, icons, text and the like that appear onsome types of user interface output devices, for example, a displaysubsystem.

User interface output devices 1420 can include a display subsystem, aprinter, a fax machine, or a non-visual communication device such asaudio and haptic devices. The display subsystem can include a cathoderay tube (CRT), a flat-panel device such as a liquid crystal display(LCD), an image projection device, or some other device for creatingvisible stimuli such as a virtual reality system. The display subsystemalso can provide non-visual stimuli such as via audio output, aromageneration, or tactile/haptic output (e.g., vibrations and forces)devices. Typically, the term ‘output device’ signifies all possibletypes of devices and processes to transfer data and information out ofcomputer system 1410 to the user or to another machine or computersystem. Such devices are connected by wire or wirelessly to a computersystem. Note: some devices transfer data and information both into andout of the computer, for example, haptic devices that generatevibrations and forces on the hand of a user while also incorporatingsensors to measure the location and movement of the hand. Technicalapplications of the sciences of ergonomics and semiotics are used toimprove the efficiency of user interactions with any processes andcomputers disclosed herein, such as any interactions with regards to thedesign and manufacture of circuits that use any of the above input oroutput devices.

Memory subsystem 1426 typically includes a number of memories includinga main random-access memory (‘RAM’) 1430 (or other volatile storagedevice) for storage of instructions and data during program executionand a read only memory (‘ROM’) 1432 in which fixed instructions arestored. File storage subsystem 1428 provides persistent storage forprogram and data files, and can include a hard disk drive, a floppy diskdrive along with associated removable media, a CD-ROM drive, an opticaldrive, a flash memory such as a USB drive, or removable mediacartridges. If computer system 1410 includes an input device thatperforms optical character recognition, then text and symbols printed onpaper can be used as a device for storage of program and data files. Thedatabases and modules used by some embodiments can be stored by filestorage subsystem 1428.

Bus subsystem 1412 provides a device for transmitting data andinformation between the various components and subsystems of computersystem 1410. Although bus subsystem 1412 is depicted as a single bus,alternative embodiments of the bus subsystem can use multiple busses.For example, a main memory using RAM can communicate directly with filestorage systems using Direct Memory Access (‘DMA’) systems.

FIG. 14B depicts a memory 1440 such as a non-transitory, processorreadable data and information storage medium associated with filestorage subsystem 1428, and/or with network interface subsystem 1416,and can include a data structure specifying a circuit design. The memory1440 can be a hard disk, a floppy disk, a CD-ROM, an optical medium,removable media cartridge, or any other medium that stores computerreadable data in a volatile or non-volatile form, such as text andsymbols on paper that can be processed by an optical characterrecognition system. A program transferred in to and out of a processorfrom such a memory can be transformed into a physical signal that ispropagated through a medium (such as a network, connector, wire, orcircuit trace as an electrical pulse); or through a medium such as spaceor an atmosphere as an acoustic signal, or as electromagnetic radiationwith wavelengths in the electromagnetic spectrum longer than infraredlight).

Detailed Description—Technology Support EDA System/Workflow Explanation

FIG. 13 depicts a set of processes 1300 used during the design,verification and fabrication of an article of manufacture such as anintegrated circuit to transform and verify design data and instructionsthat represent the integrated circuit. Each of these processes can bestructured and enabled as multiple modules. The term ‘EDA’ signifies theterm ‘Electronic Design Automation’. These processes start with thecreation of a product idea 1310 with information supplied by a designer,information which is transformed to create an article of manufacturethat uses a set of EDA processes 1312. When the design is finalized, itis taped-out 1334, which typically is when artwork (e.g., geometricpatterns) for the integrated circuit is sent to a fabrication facilityto manufacture the mask set, which is then used to manufacture theintegrated circuit. After tape-out, a semiconductor die is manufactured1336 and packaging and assembly processes 1338 are performed to producethe finished integrated circuit 740.

Specifications for a circuit or electronic structure are as used incommerce at multiple levels of useful abstraction ranging from low-leveltransistor material layouts to high-level description languages. Mostdesigners start with a description using one or more modules with lessdetail at a high-level of abstraction to design their circuits andsystems, using a hardware description language (‘HDL’) such as VHDL,Verilog, System Verilog, SystemC, MyHDL or OpenVera. The high-leveldescription is easier for designers to understand, especially for a vastsystem, and can describe very complex systems that are difficult tounderstand using a lower level of abstraction that is a more detaileddescription. The HDL description can be transformed into other levels ofabstraction that are used by the developers. For example, a high-leveldescription can be transformed to a logic-level register transfer level(‘RTL’) description, a gate-level description, a layout-leveldescription, or a mask-level description. Each lower abstraction levelthat is a less abstract description adds more useful detail into thedesign description, for example, more details for the modules thatcomprise the description. The lower-levels of abstraction that are lessabstract descriptions can be generated by a computer, derived from adesign library, or created by another design automation process. Anexample of a specification language at a lower level of abstractionlanguage for specifying more detailed descriptions is SPICE, which ismuch used for detailed descriptions of circuits with many analogcomponents. A circuit specification for a circuit also has value as anarticle of manufacture in commerce as a good under the UniformCommercial Code (see U.C.C. Article 2, Part 1). Descriptions at eachlevel of abstraction are enabled for use by the corresponding tools ofthat layer (for example, a formal verification tool), and some of themodules of the abstractions need not be novel or unobvious.

A design process that uses EDA processes 1312 includes processes 1314 to1332, which are described below. This design flow description is usedonly to illustrate, not to limit. For example, a designer of anintegrated circuit design can use the design processes in a differentsequence than the sequence depicted in FIG. 13. For the embodimentsdisclosed herein, products from Synopsys, Inc. of Mountain View, Calif.(hereinafter signified by ‘Synopsys’), are used to enable theseprocesses, and/or similar products from other companies.

During system design 1314, a designer specifies the functionality to bemanufactured. The designer also can optimize the power, performance andarea (physical and/or lines of code) and minimize costs, etc.Partitioning of the design into different types of modules can occur atthis stage. Exemplary EDA products from Synopsys that enable systemdesign 1314 include: the Model Architect, Saber, System Studio, andDesignware products.

During logic design and functional verification 1316, modules in thecircuit are specified in one or more description languages, and thespecification is checked for functional accuracy, that is, that themodules produce outputs that match the requirements of the specificationof the circuit or system being designed. Exemplary HDL languages areVerilog, VHDL and SystemC. Functional verification typically usessimulators and other programs such as test bench generators, static HDLcheckers and formal verifiers. In some situations, special systems ofmodules referred to as ‘emulators’ or ‘prototyping systems’ are used tospeed up the functional verification. Exemplary EDA products fromSynopsys that can be used at this stage include: VCS, Vera, Designware,Magellan, Formality, ESP and Leda products. Exemplary emulator andprototyping products available from Synopsys that enable logic designand functional verification 1316 include: Zebu® and Protolink® (®signifies ‘Registered Trademark’).

During synthesis and design for test 1318, HDL code is transformed to anetlist (which typically is a graph structure where the edges representcomponents of a circuit and where the nodes represent how the componentsare interconnected). Both the HDL code and the netlist are hierarchicalarticles of manufacture that can be used by an EDA product to verifythat the integrated circuit, when manufactured, performs according toits design. This netlist can be optimized for a target semiconductormanufacturing technology. Additionally, the finished integrated circuitis tested to verify that it satisfies the requirements of thespecification. Exemplary EDA products from Synopsys that enablesynthesis and design for test 718 include: the Design Compiler, PhysicalCompiler, Test Compiler, Power Compiler, FPGA Compiler, Tetramax, andDesignware products.

During netlist verification 1320, the netlist is checked for compliancewith timing constraints and for correspondence with the HDL code.Exemplary EDA products from Synopsys that enable netlist verification1320 include: the Formality, Primetime, and VCS products.

During design planning 1322, an overall floor plan for the integratedcircuit is constructed and analyzed for timing and top-level routing.Exemplary EDA products from Synopsys that enable design planning 1322include: the Astro and IC Compiler products.

During layout implementation 1324, physical placement (positioning ofcircuit components such as transistors or capacitors) and routing(connection of the components by multiple conductors) occurs, and theselection of cells from a library to enable specific logic functions. Asused herein, the term ‘cell’ signifies a set of transistors, othercomponents, and interconnections that provides a Boolean logic function(e.g., AND, OR, NOT, XOR) or a storage function (such as a flipflop orlatch). As used herein, a circuit ‘block’ comprises two or more cells.Both a cell and a circuit block can be referred to as a module, and areenabled as both physical structures and in simulations. Parameters arespecified for selected cells (based on ‘standard cells’) such as size,and made accessible in a database for use by EDA products. Examples ofdatabases that can be used for accessing cells include MySQL andPostgreSQL. Exemplary EDA products from Synopsys that enable layoutimplementation 724 include: the Astro and IC Compiler products.

During analysis and extraction 1326, the circuit function is verified atthe layout level, which permits refinement of the layout design.Exemplary EDA products from Synopsys that enable analysis and extraction726 include: the Astrorail, Primerail, Primetime, and Star RC/XTproducts.

During physical verification 1328, the layout design is checked toensure that manufacturing constraints are correct, such as DRCconstraints, electrical constraints, lithographic constraints, and thatcircuitry function matches the HDL design specification. Exemplary EDAproducts from Synopsys that enable physical verification 1328 include:the Hercules product.

During resolution enhancement 1330, the geometry of the layout istransformed to improve how the design is manufactured. Exemplary EDAproducts from Synopsys that enable resolution enhancement 1330 include:the Proteus product.

During tape-out, data is created to be used (after lithographicenhancements are applied if appropriate) for production of lithographymasks. Example EDA products from Synopsys that enable tape-out include:the IC Compiler and Custom Designer products.

During mask-data preparation 1332, the ‘tape-out’ data is used toproduce lithography masks that are used to produce finished integratedcircuits. Exemplary EDA products from Synopsys that enable mask-datapreparation 1332 include: the CATS family of products.

For all of the abovementioned EDA products, similar products from otherEDA vendors, such as Cadence, Siemens, other corporate entities orvarious non-commercial products from universities, or open sourcerepositories, can be used as an alternative.

A storage subsystem of a computer system (such as computer system 610 ofFIG. 6A) is preferably used to store the programs and data structuresthat are used by some or all of the EDA products described herein, andproducts used for development of cells for the library and for physicaland logical design that use the library.

Detailed Description—Semantic Support

The signifier ‘commercial solution’ signifies, solely for the followingparagraph, an engineering domain-specific (and thus non-preemptive—seeBilski): electronic structure, a process for a specified machine, amanufacturable circuit (and their Church-Turing equivalents) or acomposition of matter that applies science and/or technology for use incommerce to solve a technical problem.

The signifier ‘abstract’ (when used in a patent claim for any enabledembodiments disclosed herein for a new commercial solution that is ascientific use of one or more laws of nature {see Benson}, and thatsolves a problem of technology {see Diehr} for use in commerce—orimproves upon an existing solution used in commerce {see Diehr})—isprecisely defined by the inventor(s) {see MPEP 2111.01 (9^(th) edition,Rev. 08.2017)} as follows:

a) a new commercial solution is ‘abstract’ if it is not novel (e.g., itis so well known in equal prior art {see Alice} and/or the use ofequivalent prior art solutions is long prevalent {see Bilski} inscience, engineering or commerce), and thus unpatentable under 35 U.S.C.102, for example, because it is ‘difficult to understand’ {seeMerriam-Webster definition for ‘abstract’} how the commercial solutiondiffers from equivalent prior art solutions; or

b) a new commercial solution is ‘abstract’ if the existing prior artincludes at least one analogous prior art solution {see KSR}, or theexisting prior art includes at least two prior art publications that canbe combined {see Alice} by a skilled person {often referred to as a‘PHOSITA’, see MPEP 2141-2144 (9^(th) edition, Rev. 08.2017)} to beequivalent to the new commercial solution, and is thus unpatentableunder 35 U.S.C. 103, for example, because it is ‘difficult tounderstand’ how the new commercial solution differs from aPHOSITA-combination/application of the existing prior art; or

c) a new commercial solution is ‘abstract’ if it is not disclosed with adescription that enables its praxis, either because insufficientguidance exists in the description, or because only a genericimplementation is described {see Mayo} with unspecified components,parameters or functionality, so that a PHOSITA is unable to instantiatean embodiment of the new solution for use in commerce, without, forexample, requiring special programming {see Katz} (or, e.g., circuitdesign) to be performed by the PHOSITA, and is thus unpatentable under35 U.S.C. 112, for example, because it is ‘difficult to understand’ howto use in commerce any embodiment of the new commercial solution.

Detailed Description—Definitions

As used herein, the semiotic function RUD(t,p1,p2, . . . ) signifiesthat a skilled person can obtain, if needed for progressing the usefularts, a reasonably useful definition of the signifier ‘t’ that comprisesthe union of definitions of ‘t’ in one or more U.S. Patents and U.S.Patent Applications ‘p1’, ‘p2’, etc. For example, ‘RUD(substantially,9532624)’ signifies that a skilled person can obtain a reasonably usefuldefinition of ‘substantially’ as it is defined in U.S. Pat. No.9,532,624.

DEFINITIONS: RUD(substantially, 9532624).

DETAILED DESCRIPTION—CONCLUSION

The Detailed Description signifies in isolation the individual features,structures, functions, or characteristics described herein and anycombination of two or more such features, structures, functions orcharacteristics, to the extent that such features, structures, functionsor characteristics or combinations thereof are enabled by the DetailedDescription as a whole in light of the knowledge and understanding of askilled person, irrespective of whether such features, structures,functions or characteristics, or combinations thereof, solve anyproblems disclosed herein, and without limitation to the scope of theClaims of the patent. When an embodiment of a claimed inventioncomprises a particular feature, structure, function or characteristic,it is within the knowledge and understanding of a skilled person to usesuch feature, structure, function, or characteristic in connection withother embodiments whether or not explicitly described, for example, as asubstitute for another feature, structure, function or characteristic.

In view of the Detailed Description, a skilled person will understandthat many variations of the claimed inventions can be enabled, such asfunction and structure of elements, described herein while remaining inthe domain of the claimed inventions. One or more elements of anembodiment can be substituted for one or more elements in anotherembodiment, as will be understood by a skilled person. Writings aboutembodiments signify their uses in commerce, thereby enabling otherskilled people to similarly use in commerce.

This Detailed Description is fitly written to provide knowledge andunderstanding. It is neither exhaustive nor limiting of the precisestructures described, but is to be accorded the widest scope consistentwith the disclosed principles and features. A skilled person can enablemany equivalent variations. Without limitation, any and all equivalentsdescribed, signified or Incorporated by Reference in this patentapplication are specifically Incorporated by Reference into the DetailedDescription. In addition, any and all variations described, signified orIncorporated By Reference with respect to any one claimed invention andits embodiment also are included with all other claimed inventions andtheir embodiments. Any such variations include both currently knownvariations as well as future variations, for example any element usedfor enablement includes a future equivalent element that provides thesame function, regardless of the structure of the future equivalentelement.

It is intended that the domain of the set of claimed inventions andtheir embodiments be defined and judged by the following Claims andtheir equivalents. The Detailed Description includes the followingClaims, with each Claim standing on its own as a separate claimedinvention. The embodiments of the claimed inventions can have morestructure and features than are explicitly specified in the claims.

What is claimed:
 1. A computerized system, comprising: a memoryconfigured to store operations; and one or more processors configured toperform the operations, the operations comprising: sorting a subset of aplurality of endpoints for communication during a communication frame,wherein the subset of the plurality of endpoints are sorted based on avalue of service interval assigned to each endpoint of the subset of theplurality of endpoints, wherein the plurality of endpoints comprise oneor more endpoints of a first peripheral device and one or more endpointsof a second peripheral device, re-sorting the sorted subset of theplurality of endpoints based on a concurrency score of the firstperipheral device with the second peripheral device, determiningavailable bandwidth for communication with the each endpoint of thesubset of the plurality of endpoints, based on the determined availablebandwidth, determining a number of packets to be communicated with theeach endpoint of the subset of the plurality of endpoints, andgenerating a scheduling table for communicating the number of packetswith the each endpoint of the subset of the plurality of endpoints basedon the concurrency score of the first peripheral device with the secondperipheral device, wherein the generated scheduling table comprises thenumber of packets to be communicated with the each endpoint of thesubset of the plurality of endpoints and an order of communication ofthe number of packets to be communicated with the each endpoint of thesubset of the plurality of endpoints.
 2. The computerized system ofclaim 1, wherein the operations further comprise: identifying one ormore bus bandwidth domains and one or more buses between a host deviceand the first peripheral device and the host device and the secondperipheral device; ordering the one or more bus bandwidth domainsbetween the host device and the first peripheral device and the hostdevice and the second peripheral device based on proximity of the one ormore bus bandwidth domains from the host device; and comparing theordered one or more bus bandwidth domains between the host device andthe first peripheral device with the ordered one or more bus bandwidthdomains between the host device and the second peripheral device todetermine the concurrency score of the first peripheral device with thesecond peripheral device.
 3. The computerized system of claim 2, whereinthe ordered one or more bus bandwidth domains form n-tuple of bandwidthdomains.
 4. The computerized system of claim 3, wherein n represents atotal number of unique data speeds.
 5. The computerized system of claim2, wherein for the comparing the ordered one or more bus bandwidthdomains, the operations further comprise: comparing each element of afirst n-tuple of bandwidth domains between the host device and the firstperipheral device with an similarly indexed element of a second n-tupleof bandwidth domains between the host device and the second peripheraldevice; and in response to the comparison showing the compared at leastone element of the first n-tuple of bandwidth domains with the similarlyindexed element of the second n-tuple of bandwidth domains beingdifferent, determining the concurrency score of the first peripheraldevice with the second peripheral device indicating the first peripheraldevice and the second peripheral device can be concurrently served. 6.The computerized system of claim 2, wherein for the comparing theordered one or more bus bandwidth domains, the operations furthercomprise: comparing each element of a first n-tuple of bandwidth domainsbetween the host device and the first peripheral device with a similarlyindexed element of a second n-tuple of bandwidth domains between thehost device and the second peripheral device; in response to thecomparison showing the compared element of the first n-tuple ofbandwidth domains with the similarly indexed element of the secondn-tuple of bandwidth domains being different, generating a weightedsub-score for the compared element of the first n-tuple of bandwidthdomain; and generating the concurrency score of the first peripheraldevice with the second peripheral device based on the weighted sub-scorefor the compared element of the first n-tuple of bandwidth domains withthe similarly indexed element of the second n-tuple of bandwidth domainsbeing different.
 7. The computerized system of claim 6, wherein thegenerated concurrency score is a first preconfigured value, a secondpreconfigured value, or a value in between the first preconfigured valueand the second preconfigured value, wherein the first preconfiguredvalue is smaller than the second preconfigured value, and wherein thegenerated concurrency score above a preconfigured threshold valueindicates the first peripheral device and the second peripheral devicecan be concurrently served.
 8. The computerized system of claim 1,wherein for the determining the available bandwidth, the operationsfurther comprise: determining required bandwidth for communicating aplurality of packets based on a transmission speed translation factorbetween a bandwidth domain of a host device and bandwidth domain of thefirst peripheral device, wherein the transmission speed translationfactor is determined by dividing a larger speed of the bandwidth domainof the host device or the peripheral device by a smaller speed of thebandwidth domain of the host device or the first peripheral device. 9.The computerized system of claim 8, wherein for the determining theavailable bandwidth, the operations further comprise: determining usedbandwidth for communicating the plurality of packets based ontransmission speed translation factors of one or more bandwidth domainsbetween a host device and the first peripheral device; and determining adifference of the required bandwidth and the used bandwidth as theavailable bandwidth.
 10. A method, comprising: sorting a subset of aplurality of endpoints for communication during a communication frame,wherein the subset of the plurality of endpoints are sorted based on avalue of service interval assigned to each endpoint of the subset of theplurality of endpoints, wherein the plurality of endpoints comprise oneor more endpoints of a first peripheral device and one or more endpointsof a second peripheral device; re-sorting the sorted subset of theplurality of endpoints based on a concurrency score of the firstperipheral device with the second peripheral device; determiningavailable bandwidth for communication with the each endpoint of thesubset of the plurality of endpoints; based on the determined availablebandwidth, determining a number of packets to be communicated with theeach endpoint of the subset of the plurality of endpoints; andgenerating a scheduling table for communicating the number of packetswith the each endpoint of the subset of the plurality of endpoints basedon the concurrency score of the first peripheral device with the secondperipheral device, wherein the generated scheduling table comprises thenumber of packets to be communicated with the each endpoint of thesubset of the plurality of endpoints and an order of communication ofthe number of packets to be communicated with the each endpoint of thesubset of the plurality of endpoints.
 11. The method of claim 10,further comprising: identifying one or more bus bandwidth domains andone or more buses between a host device and the first peripheral deviceand the host device and the second peripheral device; ordering the oneor more bus bandwidth domains between the host device and the firstperipheral device and the host device and the second peripheral devicebased on proximity of the one or more bus bandwidth domains from thehost device; and comparing the ordered one or more bus bandwidth domainsbetween the host device and the first peripheral device with the orderedone or more bus bandwidth domains between the host device and the secondperipheral device to determine the concurrency score of the firstperipheral device with the second peripheral device.
 12. The method ofclaim 11, wherein the ordered one or more bus bandwidth domains formn-tuple of bandwidth domains.
 13. The method of claim 12, wherein nrepresents a total number of unique data speeds.
 14. The method of claim11, wherein the comparing the ordered one or more bus bandwidth domainscomprises: comparing each element of a first n-tuple of bandwidthdomains between the host device and the first peripheral device with ansimilarly indexed element of a second n-tuple of bandwidth domainsbetween the host device and the second peripheral device; and inresponse to the comparison showing the compared at least one element ofthe first n-tuple of bandwidth domains with the similarly indexedelement of the second n-tuple of bandwidth domains being different,determining the concurrency score of the first peripheral device withthe second peripheral device indicating the first peripheral device andthe second peripheral device can be concurrently served.
 15. The methodof claim 11, wherein the comparing the ordered one or more bus bandwidthdomains comprises: comparing each element of a first n-tuple ofbandwidth domains between the host device and the first peripheraldevice with a similarly indexed element of a second n-tuple of bandwidthdomains between the host device and the second peripheral device; inresponse to the comparison showing the compared element of the firstn-tuple of bandwidth domains with the similarly indexed element of thesecond n-tuple of bandwidth domains being different, generating aweighted sub-score for the compared element of the first n-tuple ofbandwidth domains; and generating the concurrency score of the firstperipheral device with the second peripheral device based on theweighted sub-score for the compared element of the first n-tuple ofbandwidth domains with the similarly indexed element of the secondn-tuple of bandwidth domains being different.
 16. The method of claim15, wherein the generated concurrency score is a first preconfiguredvalue, a second preconfigured value, or a value in between the firstpreconfigured value and the second preconfigured value, wherein thefirst preconfigured value is smaller than the second preconfiguredvalue, and wherein the generated concurrency score above a preconfiguredthreshold value indicates the first peripheral device and the secondperipheral device can be concurrently served.
 17. The method of claim10, wherein the determining the available bandwidth comprises:determining required bandwidth for communicating a plurality of packetsbased on a transmission speed translation factor between a bandwidthdomain of a host device and bandwidth domain of the first peripheraldevice, wherein the transmission speed translation factor is determinedby dividing a larger speed of the bandwidth domain of the host device orthe peripheral device by a smaller speed of the bandwidth domain of thehost device or the first peripheral device.
 18. The method of claim 17,wherein the determining the available bandwidth further comprises:determining used bandwidth for communicating the plurality of packetsbased on transmission speed translation factors of one or more bandwidthdomains between a host device and the first peripheral device; anddetermining a difference of the required bandwidth and the usedbandwidth as the available bandwidth.
 19. A non-transitory, tangiblecomputer-readable device having instructions stored thereon that, whenexecuted by at least one computing device, causes the at least onecomputing device to perform operations comprising: sorting a subset of aplurality of endpoints for communication during a communication frame,wherein the subset of the plurality of endpoints are sorted based on avalue of service interval assigned to each endpoint of the subset of theplurality of endpoints, wherein the plurality of endpoints comprise oneor more endpoints of a first peripheral device and one or more endpointsof a second peripheral device; re-sorting the sorted subset of theplurality of endpoints based on a concurrency score of the firstperipheral device with the second peripheral device; determiningavailable bandwidth for communication with the each endpoint of thesubset of the plurality of endpoints; based on the determined availablebandwidth, determining a number of packets to be communicated with theeach endpoint of the subset of the plurality of endpoints; andgenerating a scheduling table for communicating the number of packetswith the each endpoint of the subset of the plurality of endpoints basedon the concurrency score of the first peripheral device with the secondperipheral device.
 20. The non-transitory, tangible computer-readabledevice of claim 19, wherein the generated scheduling table comprises thenumber of packets to be communicated with the each endpoint of thesubset of the plurality of endpoints and an order of communication ofthe number of packets to be communicated with the each endpoint of thesubset of the plurality of endpoints.